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FEATURES 192-Bit Pixel Port Allows 2048 2048 24 Screen Resolution 360 MHz, 24-Bit True-Color Operation Triple 8-Bit D/A Converters 8:1 Multiplexing Onboard PLL RS-343A/RS-170 Compatible Analog Outputs TTL Compatible Digital Inputs Internal Voltage Reference Standard 8-Bit MPU I/O Interface DAC-DAC Matching: Typ 2%, Adjustable to 0.02% +5 V CMOS Monolithic Construction 304-Pin PQFP Package APPLICATIONS Ultrahigh Resolution Color Graphics Image Processing Drives 24-Bit Color 2K 2K Monitors
192-Bit, 360 MHz True-Color Video DAC with Onboard PLL ADV7129
GENERAL DESCRIPTION
The ADV7129 is a complete analog output, video DAC on a single CMOS (ADV(R)) monolithic chip. The part is specifically designed for use in the highest resolution graphics and imaging systems. The ultimate level of integration, comprised of 360 MHz triple 8-bit DACs, a programmable pixel port, an internal voltage reference and an onboard PLL, makes the ADV7129 the only choice for the very highest level of performance and functionality. The device consists of three high speed, 8-bit, video D/A converters (RGB). An onboard phase locked loop clock generator is provided to provide high speed operation without requiring high speed external crystal or clock circuitry. The part is fully controlled through the MPU port by the onboard command registers. This MPU port may be updated at any time without causing sparkle effects on the screen.
ADV is a registered trademark of Analog Devices, Inc.
(continued on page 10)
FUNCTIONAL BLOCK DIAGRAM
VAA
VSYNC HSYNC CSYNC BLANK ODD/EVEN 24 A 24 B 24 C PIXEL DATA (RED, GREEN, BLUE) 24 D 24 E 24 F 24 G 24 H LOADIN LPF PLL INT PIXEL CLOCK 8 MUX 8:1 8 8
BLANK AND SYNC LOGIC
SENSE/SYNCOUT
RED DAC
IOR IOR
GREEN DAC
IOG IOG
BLUE DAC
IOB IOB
ADV7129
VREF RRSET RGSET RBSET RCOMP GCOMP BCOMP 8
VOLTAGE REFERENCE CONTROL REGISTERS MPU PORT
CLOCK CONTROL
LOADOUT
CE R/W C0 C1
D7-D0
GND
ADV is a registered trademark of Analog Devices, Inc..
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
ADV7129-SPECIFICATIONS
All Versions STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity Gray Scale Error DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance ANALOG OUTPUTS Gray Scale Current Range Output Current White Level Relative to Black Black Level Relative to Blank Blank Level, Sync Disabled LSB Size DAC to DAC Matching Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Voltage Reference Range, VREF Input Current, IVREF POWER REQUIREMENTS VAA IAA4 IAA4 Power Supply Rejection Ratio DYNAMIC PERFORMANCE Clock and Data Feedthrough5 Glitch Impulse DAC to DAC Crosstalk6
3
(VAA1 = +5 V, VREF = +1.235 V, RRSET, RGSET, RBSET = 280 , RL = 25 All specifications TMIN to TMAX2 unless otherwise noted.)
Min Typ Max 8 1 1 5
, CL = 10 pF.
Units Bits LSB LSB % Gray Scale Binary Coding V V A pF V V A pF mA mA mA A A % V k pF V A V mA mA %/% dB pV secs dB
Conditions1
Guaranteed Monotonic
2.0 GND - 0.5 VIN = 0.4 V or 2.4 V 10 IOH = -400 A IOL = 3.2 mA 2.4
VAA + 0.5 0.8 10
0.4 10 10 10 50.16 4.1 0 52.80 4.32 5 223 2 10 20 60 55.44 4.54 50 5 1.4
0
VREF = 1.234 V for Specified Performance
1.14
1.235 5 5 160 360 0.12 -30 50 -23
1.30
Analog Current Digital Current @ 360 MHz
200 400
NOTES 1 5% for all versions. 2 Temperature range (TMIN to TMAX), 0C to +70C, TJ (Silicon Junction Temperature) 100oC. 3 Static performance is measured with the Gain Error Registers set to 00H (disabled). 4 IAA is measured with a typical dynamic pattern, satisfying the absolute maximum current spec for the DACs. 5 Clock and Data Feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. TTL input values are 0 V to 3 V, with input rise/fall times 3 ns, measured at the 10% and 90% points. Timing reference points are at 50% for inputs and outputs. 6 DAC to DAC crosstalk is measured by holding one DAC high while the other two DACs are making low to high and high to low transitions. Specifications subject to change without notice.
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ADV7129 TIMING SPECIFICATIONS All specifications T
Parameter CLOCK CONTROL & PIXEL PORT LOADIN Clocking Rate, fLCLK LOADIN Cycle Time, t1 LOADIN Low Time, t2 LOADIN High Time, t3 LOADIN to LOADOUT Delay, t4 Pixel Setup Time, t5 Pixel Hold Time, t6
4
(VAA2 = +5 V, VREF = +1.235 V, RRSET, RGSET, RBSET = 280 , RL = 25 3 MIN to TMAX unless otherwise noted.)
Conditions Min 10 16.67 6.67 6.67 1 4 10 10 25 25 2 1
for IOG, IOR, IOB, CL = 10 pF.
Typ Max 45 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns PCLKs ps rms
5 0 2 2.5 0.5
MPU PORT R/W, C0, C1 Setup Time, t7 R/W, C0, C1 Hold Time, t8 CE Low Time, t9 CE High Time, t10 CE Asserted to Data-Bus Driven, t11 CE Asserted to Data-Bus Valid, t12 CE Negated to Data-Bus Invalid, t13 CE Negated to Data-Bus Three Stated, t14 Write Data (D7-D0) Setup Time, t15 Write Data (D7-D0) Hold Time, t16 ANALOG OUTPUTS5 Analog Output Delay, t17 Analog Output Rise/Fall Time, t18 Analog Output Transition Time, t19 RGB Analog Output Skew, tSK Pipeline Delay, tPD PLL PERFORMANCE6 Jitter (1) @ 360 MHz
5 20 15
10 10 5 0.8 25 1.5 19 (LOADIN = 45 MHz) 55
NOTES 1 TTL inputs values are 0 V to 3 V with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load 10 pF. Databus (D7-D0) loaded as shown in Figure 1. Digital output load for SENSE 30 pF. 2 5% for all versions. 3 Temperature range (T MIN to TMAX), 0C to +70C. 4 Pixel Port consists of the following inputs: Pixel Inputs: RED [A-H], BLUE [A-H], GREEN [A-H]. 5 Output Delay is measured from the 50% rising edge of LOADIN to the 50% point of full-scale transition on the A pixel. t17 includes the analog delay due to DACs and internal gate transitions plus the pipeline stages delay. The output delay for pixels B-H will be the output delay to the A pixel (t 17) plus the appropriate number of clock cycles. Output rise/fall time is measured between the 10% and 90% points of full-scale transition. Settling time is measured from the 50% point of full-scale transition to the output remaining within 1%. (Settling Time does not include clock and data feedthrough.) 6 Jitter is measured by triggering on the output clock, delayed by 15 s and then measuring the time period from the trigger edge to the next edge of the output clock after the delay. This measurement is repeated multiple times and the rms value is determined. Specifications subject to change without notice.
ISINK
TO OUTPUT PIN 100pF
+2.1V
ISOURCE
Figure 1. LOADIN vs. Pixel Input Data
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ADV7129
t4 LOADOUT
t1
LOADIN
t2
PIXEL INPUT DATA
t3
AN ... HN
AN+1 ... HN+1
AN+2 ... HN+2
DIG IT OUT AL INP UT PUT PIPE TO AN LINE ALO G
ANALOG OUTPUT DATA AN-1 ... HN-1 AN ... HN AN+1 ... HN+1 AN+2 ... HN+2
t PD
Figure 2. LOADIN vs. Pixel Input Data
t7
R/W, C0, C1
t8
VALID CONTROL DATA
t9
CE
t12
D7-D0 (READ MODE)
t10 t13
R/W = 1
t11
t14
D7-D0 (WRITE MODE) R/W = 0
t15
t16
Figure 3. Microprocessor Port (MPU) Interface Timing
PCLK
t17
t19
WHITE LEVEL
ANALOG OUTPUTS
IOR IOG IOB SYNCOUT
90 %
50 %
FULL-SCALE TRANSITION
10 %
t18
BLACK LEVEL
NOTE: THIS DIAGRAM IS NOT TO SCALE. FOR THE PURPOSES OF CLARITY, THE ANALOG OUTPUT WAVEFORM IS MAGNIFIED IN TIME AND AMPLITUDE W.R.T THE CLOCK WAVEFORM. SYNCOUT IS A DIGITAL VIDEO OUTPUT SIGNAL. t17 IS THE ONLY RELEVENT TIMING SPECIFICATION FOR SYNCOUT.
Figure 4. Analog Output Response vs. LOADIN
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ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE*
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Pin . . . . GND - 0.5 V to VAA + 0.5 V Ambient Operating Temperature (TA) . . . . . . . . 0C to +70C Storage Temperature (TS) . . . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +260C Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . +220C Analog Outputs to GND2 . . . . . . . . . . . GND - 0.5 V to VAA Current on Any DAC Output . . . . . . . . . . . . . . . . . . . . 60 mA
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration.
Model ADV7129KS
Temperature Range 0C to +70C
Package Option S-304
*Due to the specialized nature and application of this part, it is not automatically available to order. Please contact your local sales office for details.
304-LEAD PQFP PIN CONFIGURATION
228 229 ROW C 153 152
ADV7129
ROW D PQFP TOP VIEW (Not to Scale) ROW B
PIN NO. 1 IDENTIFIER 304 1 ROW A 76
77
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7129 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN ASSIGNMENTS
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
*No Connect.
Mnemonic GND GND GND GND GND GND R0E R0D R0C R0B R0A G7H G7G G7F G7E G7D G7C G7B G7A G6H G6G G6F G6E G6D G6C G6B G6A G5H G5G G5F G5E G5D G5C G5B G5A G4H G4G G4F G4E G4D
Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Mnemonic G4C G4B G4A VAA GND VAA GND G3H G3G G3F G3E G3D G3C G3B G3A G2H G2G G2F G2E G2D G2C G2B G2A G1H G1G G1F G1E G1D G1C G1B GND GND GND GND GND GND GND GND GND GND
Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Mnemonic GND GND G1A G0H G0G G0F G0E G0D G0C G0B G0A B7H B7G B7F B7E B7D B7C B7B B7A B6H B6G B6F B6E B6D B6C B6B B6A B5H B5G B5F B5E B5D B5C B5B B5A VAA GND B4H B4G B4F
Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Mnemonic B4E B4D B4C B4B B4A B3H B3G B3F B3E B3D B3C B3B B3A B2H B2G B2F B2E B2D B2C B2B B2A B1H B1G B1F B1E B1D GND GND GND GND GND GND GND GND GND GND GND GND B1C B1B
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Pin No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196
*No Connect.
Mnemonic B1A B0H B0G B0F B0E B0D B0C B0B B0A BLANK HSYNC VSYNC ODD/EVEN NC* GND GND IOB IOB RBSET BCOMP VAA VAA BBIAS IOG IOG RGSET GCOMP VAA VAA GBIAS IOR IOR RRSET RCOMP VAA VAA
Pin No. 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232
Mnemonic RBIAS SENSE/SYNCOUT VREF GND D0 D1 D2 D3 GND VAA D4 D5 D6 D7 CE R/W C0 C1 R7H R7G R7F R7E R7D R7C R7B R7A GND GND GND GND GND GND GND GND GND GND
Pin No. 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268
Mnemonic GND GND R6H R6G R6F R6E R6D R6C R6B R6A R5H R5G R5F VAA GND VAA GND R5E R5D R5C R5B R5A R4H R4G R4F R4E R4D R4C GND GND VAA LPF GND LOADIN GND CSYNC
Pin No. 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304
Mnemonic LOADOUT R4B R4A R3H R3G R3F R3E R3D R3C R3B R3A R2H R2G R2F R2E R2D R2C R2B R2A R1H R1G R1F R1E R1D R1C R1B R1A R0H R0G R0F GND GND GND GND GND GND
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ADV7129
PIN DESCRIPTION
Mnemonic R7-R0[A . . . H] G7-G0[A . . . H] B7-B0[A . . . H] BLANK
Function Red Pixel Port Inputs (TTL Compatible Inputs). Eight sets of eight bits latched on the rising edge of LOADIN. Green Pixel Port Inputs (TTL Compatible Inputs). Eight sets of eight bits latched on the rising edge of LOADIN. Blue Pixel Port Inputs (TTL Compatible Inputs). Eight sets of eight bits latched on the rising edge of LOADIN. Composite Blank (TTL Compatible Input). This video control signal drives the analog outputs to the blanking level. When BLANK is at logic "0," the pixel inputs are ignored. Pedestal selection is controlled by Bit CR15 of Command Register 1. BLANK is latched on the rising edge of LOADIN. Odd/Even Field Input (TTL Compatible Input). This input indicates which field of the frame is being displayed. An even field is selected by setting ODD/EVEN to logical "0." An odd field is selected by setting ODD/EVEN to logical "1." ODD/EVEN should be changed only during vertical blank. Horizontal-Sync Input (TTL Compatible Input). This control signal is latched on the rising edge of LOADIN. Vertical-Sync Input (TTL Compatible Input). This control signal is latched on the rising edge of LOADIN. Composite-Sync Input (TTL Compatible Input). This video control signal drives the analog outputs to the SYNC level. It is only asserted during the blanking period and does not override any other control or data input. CR14, CR13 or CR12 of Command Register 1 must be set together with CR11 or Command Register 1 to decode SYNC onto the IOR/IOR, IOG/IOG or IOB/IOB analog outputs, otherwise the SYNC input is ignored. Chip Enable Input (TTL Compatible Input). This input must be set to logic "0" when writing or reading over the data bus (D7-D0). Internally, data is latched on the rising edge of CE. Read/Write pin (TTL Compatible Input). This signal is latched on the falling edge of CE. A high level indicates a read operation and a low level indicates a write operation. Register select pins (TTL Compatible Inputs). These inputs select which MPU port register is selected for writing or reading. Data is latched on the falling edge of CE. Data Bus (TTL Compatible Input/Output Bus). Data, including color palette values and device control information is written to and read from the device over this 8-bit, bidirectional databus. Any unused bits of the data bus should be terminated through a resistor to either the digital power plane (VCC) or GND. Pixel Data Load Input (TTL Compatible Input). This input latches the multiplexed pixel data, including BLANK, HSYNC, VSYNC, CSYNC, and ODD/EVEN into the device. This rising edge of this signal is used to latch in the video signal inputs. It is also used as a reference frequency to generate an 8 x multiple pixel clock using the fixed reference onboard PLL. Pixel Data Load Output (TTL Compatible Output). This digital output is PCLK/8. If the onboard phase lock loop is used, it has the same phase as LOADIN. Low-Pass Filter Pin. This pin stabilizes the internal PLL. The following network is recommended.
VAA
ODD/EVEN
HSYNC VSYNC CSYNC
CE R/W C0, C1 D7-D0
LOADIN
LOADOUT LPF
0.1F 0.001F 100
LPF
Figure 5.
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ADV7129
Mnemonic IOR, IOG, IOB IOR, IOG, IOB Function Red, Green & Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into doubly terminated 50 or 75 loads. Differential Red, Green & Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into doubly terminated 50 or 75 loads. If the complementary outputs are not required, then these outputs should be tied to GND. Red Compensation pin. This pin should be bypassed to VAA with 0.01 F capacitor. Green Compensation pin. This pin should be bypassed to VAA with 0.01 F capacitor. Blue Compensation pin. This pin should be bypassed to VAA with 0.01 F capacitor. DAC Output Full-Scale Adjust Control (Analog Input): A resistor from this pin to ground sets the current in the DACs. The current in the DACs is set according to the equations: IOUT = 12,950 x VREF/RSET (SYNC not encoded on the DAC Output) IOUT = 18,137 x VREF/RSET (SYNC encoded on the DAC Output) To generate RS 343-A video levels on the DAC outputs, a resistor value of 280 is recommended for doubly terminated 50 lines. Any combination of RSET value, DAC termination resistor and programming of SYNC and pedestal are possible provided that the maximum DAC current and the DAC output compliance specifications are adhered to. For example, in a doubly terminated 50 system with no SYNC or pedestal encoded on the DAC outputs, an RSET value of 280 gives a DAC full-scale output of 52.8 mA, i.e., a white-to-black value of 1.4 V. This example would give a 6 dB reduction in noise and feedthrough on the DAC outputs (compared to a 0.7 V full-scale value), but may require a 0.5X splitter at the monitor. RBIAS GBIAS BBIAS SENSE/SYNCOUT Red Bias node. This node should be decoupled to VAA with a 0.01 F capacitor. Green Bias node. This node should be decoupled to VAA with a 0.01 F capacitor. Blue Bias node. This node should be decoupled to VAA with a 0.01 F capacitor. Comparator Sense Output (TTL Compatible Output). This output will be logic "1" if one or more of the analog outputs exceeds the internal voltage of the SENSE comparator circuit. It can be used to determine the absence of a CRT monitor. The value of the SENSE Output corresponds to the current pixel at the outputs. The output can drive one CMOS load. This pin can alternately be programmed to be a TTL sync output which is a delayed version of CSYNC. Voltage Reference (Analog Input/Output): This should always have a 0.1 F decoupling capacitor attached between VREF and VAA. If nothing else is connected then the DACs are driven by the internal voltage reference. If it is required to use a more accurate reference, then this pin acts as an overdrive input. An external 1.235 V voltage reference such as the AD1580 or equivalent is recommended to drive this input. (Note: It is not recommended to use a resistor network to generate the voltage reference.) Power Supply (+5 V 5%). The part contains multiple power supply pins, all should be connected together to one common +5 V filtered analog power supply. Analog Ground. The part contains multiple ground pins, all should be connected together to the system's ground plane.
RCOMP GCOMP BCOMP RRSET, RGSET, RBSET
VREF
VAA GND
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ADV7129
(continued from page 1) The ADV7129 supports 24-bit true-color formats where screen resolution is the primary design goal. The individual Red, Green and Blue pixel input ports allow true-color image rendition at resolutions of 2048 x 2048 x 24 bit. The ADV7129 is capable of generating RGB video output signals that are compatible with RS-343A and RS-170 video standards, without requiring external buffering. An internal voltage reference is also provided to simplify system design. The ADV7129 is fabricated in a +5 V CMOS process. The ADV7129 is packaged in a 304-pin PQFP package.
CIRCUIT DETAILS AND OPERATION SENSE
If any one or more of the analog outputs, IOG, IOR and IOB, exceed the internal voltage reference level (due to absence of CRT), SENSE is set to logic "1." The SENSE output can drive one CMOS load and can be used to determine the absence of a CRT monitor.
CLOCK CONTROL CIRCUIT
The ADV7129 has an integrated clock control circuit. This circuit is capable of generating the internal clocking signals. A lower frequency external clock generator is used by enabling the onboard PLL. This fixed multiple PLL is used to speed up LOADIN by a factor of 8. This onboard 8 x clock multiplier is activated by setting Bit CR20 of Command Register 2 from logic "0" to logic "1." It must be set up after power-up.
MICROPROCESSOR (MPU) PORT
Digital video or pixel data is latched into the ADV7129 over the pixel port. The data is multiplexed and latched into the three 8bit digital-to-analog converters (DACs) and output as an RGB video signal. The ADV7129 can be broken into three sections for purposes of clarity of explanation: 1. Pixel port and clock control circuit. 2. MPU port, registers and cursor. 3. Digital-to-analog converters and video outputs.
Pixel Port and Clock Circuits
The ADV7129 supports a standard MPU interface. All the functions of the part are controlled via this MPU port. Direct access is gained to the address register and all the control registers as well as the cursor palette. The following sections describe the setup for reading and writing to all of the devices' registers.
MPU Interface
The pixel port of the ADV7129 is directly interfaced to the video/graphics pipeline of a computer graphics subsystem. It is connected directly through a gate array to the video RAM of the system's frame buffer. The pixel port of the ADV7129 consists of: Color Data: Pixel Controls: Clock Input Clock Output RED, GREEN, BLUE HSYNC, VSYNC, CSYNC, BLANK LOADIN LOADOUT
The MPU interface consists of a bidirectional, 8-bit wide databus and interface control signals R/W, CE, C1, C0. Two write operations are required to set up the lower 8 bits and higher 2 bits of the Address Register.
Register Mapping
The associated clocking signals for the pixel port include:
The ADV7129 contains a number of onboard registers including the Address Register, Command Registers and Gain Error Registers. Control Lines C1-C0 determine whether the Address Register is being pointed to (upper or lower bytes) or whether the other registers are being accessed. The R/W and CE control inputs allow read and write access. All registers can to read and written to.
Power-On Reset
Pixel Port (Color Data)
The ADV7129 has 192 color data inputs. This supports 24-bit true color with 8:1 multiplexing. Color data is always latched on the rising edge of LOADIN. LOADOUT is generated internally by the ADV7129. The frequency of LOADOUT is the internal clock frequency (PCLK) divided by 8. Other pixel data signals latched into the part by LOADIN include HSYNC, BLANK, VSYNC and CSYNC.
HSYNC, VSYNC, CSYNC, BLANK
After power-up, the ADV7129 must be set to perform a reset operation. This is achieved by resetting the PLL (a low to high transition on Bit CR20 of Command Register 2). This initializes the pixel port such that the pixel sequence ABCDEFGH starts at A. This reset can be performed as the registers are being initialized. The Command Registers power up in an indeterminate state and must be set up for the required operation. The power-on is activated when VAA goes from 0 V to 5 V. This is active for 1 s. The ADV7129 should not be accessed during this period.
Register Accesses
The BLANK and SYNC video control signals drive the analog outputs to the blanking and sync levels respectively. These are latched on the rising edge of LOADIN. The SYNC information can be encoded onto any of the IOG, IOR or IOB analog outputs by setting Bits CR12, CR13 or CR14 of Command Register 1 to logic "1." The SYNC information is ignored if Bits CR12, CR13 and CR14 of Command Register 1 are set to logic "0." The SYNC and BLANK information can be decoded onto the inverted outputs by setting CR10 and CR11 of Command Register 1 to logic level "1."
The MPU can write to or read from all of the ADV7129s' registers. Figure 6 shows the Control Registers and C1-C0 Control Input Truth Table. The read/write timing is controlled by the CE and R/W inputs. The Address Register determines which Control Register is being accessed. The registers can be addressed directly by two write cycles to set up the high and low bytes of Address Register and then by a read or write cycle of the MPU.
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ADV7129
REGISTER PROGRAMMING
The following section describes each register, including Address Register and each of the Control Registers in terms of its configuration.
Address Register (A10-A0)
COMMAND REGISTER 1 (CR1) (Address Register (A10-A0) = 400H)
This register contains a number of control bits as shown in the diagram. CR1 is an 8-bit wide register. Figure 7 shows the various operations under the control of CR1. This register can be read from as well as written to. Bit CR16 is reserved and should be set to logic "1."
COMMAND REGISTER 1-BIT DESCRIPTION
As illustrated previously, the C1-C0 inputs, in conjunction with the Address Register specify which control register, or palette RAM location is accessed by the MPU port. The Address Register is 16 bits wide and can be read from as well as written to.
CONTROL REGISTERS
A large bank of registers can be accessed using the Address register and C1-C0. Access is made first by writing the Address Register with the appropriate address to point to the particular Control Register, and then performing an MPU access to the Control Register.
ADDRESS REGISTER (A10-A0) C1 0 0 1 0 0 1 1 (A10-A0) 4FF-412 411 410 40F 40E 40D 40C 40B 40A 409 408 407 406 405 004 403 402 401 400 000-3FF C0 0 1 0 0 1 0 1 R/W 0 0 0 1 1 1 X WRITE TO ADDRESS REGISTER (LOWER BYTE) WRITE TO ADDRESS REGISTER (UPPER BYTE) WRITE TO REGISTERS READ FROM ADDRESS REGISTER (LOWER BYTE) READ FROM ADDRESS REGISTER (UPPER BYTE) READ FROM REGISTERS RESERVED
BLANK Control on Inverted Outputs (CR10): This bit specifies whether the video BLANK is to be decoded onto the inverted analog outputs or ignored.
SYNC Control on Inverted Outputs (CR11)
This bit specifies whether the video SYNC is to be decoded onto the inverted analog outputs or ignored.
SYNC Recognition on Blue (CR12)
This bit specifies whether the video SYNC input is to be decoded onto the IOB analog output or ignored.
SYNC Recognition on Green (CR13)
This bit specifies whether the video SYNC input is to be decoded onto the IOG analog output or ignored.
SYNC Recognition on Red (CR14)
REGISTER ACCESS RESERVED COMMAND REGISTER 2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BLUE DAC GAIN ERROR REGISTER GREEN DAC GAIN ERROR REGISTER RED DAC GAIN ERROR REGISTER RESERVED RESERVED RESERVED RESERVED COMMAND REGISTER 1 RESERVED
This bit specifies whether the video SYNC input is to be decoded onto the IOR analog output or ignored.
Pedestal Enable Control (CR15)
This bit specifies whether a 0 IRE or a 7.5 IRE blanking pedestal is to be generated on the video outputs.
Display Mode Control (CR17)
This bit controls whether the display is interlaced or noninterlaced.
Figure 6. Control Registers
CR17 CR16 CR15 CR14 CR13 CR12 CR11 CR10
INTERLACE ENABLE CR17 0 1 DISABLE ENABLE
PEDESTAL ENABLE CONTROL CR15 0 1 0 IRE 7.5 IRE
SYNC RECOGNITION CONTROL (IOB) CR12 0 1 SYNC RECOGNITION CONTROL (IOG) CR13 0 1 IGNORE DECODE CR11 0 1 IGNORE DECODE IGNORE DECODE
PEDESTAL CONTROL (IOR, IOG, IOB) CR10 0 1 DISABLE BLANK ON INVERTED OUTPUTS DECODE BLANK ON INVERTED OUTPUTS
CR16 = 0 (RESERVED) ZERO MUST BE WRITTEN TO THIS BIT
SYNC CONTROL (IOR, IOG, IOB)
SYNC RECOGNITION CONTROL (IOR) CR14 0 1
DISABLE SYNC ON INVERTED OUTPUTS DECODE SYNC ON INVERTED OUTPUTS
Figure 7. Command Register 1
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ADV7129
COMMAND REGISTER 2 (CR2) (Address Register (A10-A0) = 411H) VCO Override Bit (CR26)
This register contains a number of control bits as shown in the diagram. CR2 is an 8-bit wide register. CR27, CR24, CR22 and CR21 are reserved and should be set to logic "0." Figure 8 shows the various operations under the control of CR2. This register can be read from as well as written to.
COMMAND REGISTER 2-BIT DESCRIPTION PLL Control (CR20)
This bit is used to override the VCO and set the PLL to the lowest frequency possible. If the external LOADIN source takes some time before it reaches its required frequency, the internal PLL can become unstable as it tries to track to a varying LOADIN signal. The VCO override bit can be set to logic level "0" and then released (set to logic level "1") to allow the VCO to track to the input after it has stabilized. It is required to allow 200 s before the VCO override bit is released.
GAIN ERROR REGISTERS (Address Register (A10-A0) = 405H-407H)
This bit resets the PLL divider when set to logic "0" and releases it when set to logic "1."
SYNCOUT Control (CR23)
This bit is an enable for SYNCOUT. If this bit is set to logic "1," the SENSE output becomes a pipelined version of CSYNC. Otherwise the SENSE output remains unaffected.
SENSE Bit (CR25)
This output bit is used to determine the absence of a CRT monitor. When CR25 is set to logic "1," a CRT is not present. With some diagnostic code, the presence of loading on the individual RGB lines can be determined. The reference is generated by a voltage divider from the external voltage reference on the VREF pin. For the proper operation, the following levels should be applied to the comparator by the IOR, IOG and IOB outputs: DAC Low Voltage 250 mV. DAC High Voltage 450 mV.
CR27 CR26 CR25 CR24
The Red, Green and Blue Gain Error Registers allow the user to compensate for any channel-to-channel variations in the video output system. They control internal resistors from each of the three DAC outputs to GND, i.e., they appear in parallel with the external termination resistor across the DAC outputs. This allows the RGB output voltages to be adjusted as the value of RINT is varied. A logic "1" on any of the control bits GR06 to GR00 switches in the appropriate resistor. A logic "0" disables or open circuits the resistor. Bit GR07 of the Gain Error Register enables or disables the Gain Error Adjust. Figure 9 shows the typical resistor values for these internal resistances versus RSET.
CR23
CR22
CR21
CR20
RESERVED (CR27) THIS BIT SHOULD BE SET TO LOGIC "0"
SENSE OUTPUT CR25 0 1 MONITOR PRESENT MONITOR NOT PRESENT
SYNCOUT CONTROL CR23 0 1 IGNORE DECODE RESERVED (CR22, CR21) THESE BITS SHOULD BE SET TO LOGIC "0"
PLL RESET CR20 0 1 RESET PLL RELEASE PLL
VCO OVERRIDE CR26 0 1 VCO OVERRIDE NORMAL PLL OPERATION
RESERVED (CR24) THIS BIT SHOULD BE SET TO LOGIC "0"
Figure 8. Command Register 2
INTERNAL RESISTORS R5 R4 R3 R2 R1
R6 DACs
R0
IOUT PIN RT1
(CABLE)
RT2 (MONITOR)
RSET
1
x
x
x
x
x
x
x
GAIN ERROR REGISTER GR07 GR06 GR05 GR04 GR03 GR02 GR01 GR00
GAIN ERROR CONTROL GR07 0 1 DISABLE GAIN ERROR ADJ ENABLE GAIN ERROR ADJ
REGISTER GR06 GR05 GR04 GR03 GR02 GR01 GR00 R6 R5 R4 R3 R2 R1 R0
(RESET = 280) 47 923 1926 3476 6979 16610 27037
Figure 9. Gain Error Register
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ADV7129
DIGITAL-TO-ANALOG CONVERTERS (DACS) AND VIDEO OUTPUTS
The ADV7129 contains three high speed video DACs. The DAC outputs are represented as the three primary analog color signals IOR (red video), IOG (green video) and IOB (blue video).
DACs and Analog Outputs
The part contains three matched 8-bit digital-to-analog converters. The DACs are designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are routed to either IOR, IOG, IOB (bit = "1") or IOR, IOG, IOB (bit = "0"). Normally IOR, IOG, & IOB are connected to GND.
IOR, IOG, IOB DACs ZS = 50 (SOURCE TERMINATION) ZO = 50 (CABLE) ZL = 50 (MONITOR)
A resistor RSET is connected between the RSET (RRSET, RGSET, RBSET) input of the part and ground. An RSET value of 280 corresponds to the generation of two times RS-343A video levels into a doubly-terminated 50 load. Figure 11 illustrates the resulting video waveform and the Video Output Truth Table illustrates the corresponding control input stimuli. On the ADV7129 SYNC can be encoded on any of the analog signals, however in practice, SYNC is generally encoded on either the IOG output or on all of the video outputs. Any combination of RSET, DAC termination resistors and programming of SYNC and pedestal are possible provided that the maximum DAC current of 60 mA and the DAC output compliance specifications are adhered to. The following tables show the current levels for different values of RSET resistors and RLOAD termination.
WHITE LEVEL
Figure 10. DAC Output Termination (Doubly Terminated 50 Load)
The analog video outputs are high impedance current sources. Each of the these three RGB current outputs are specified to directly drive a 25 load (doubly-terminated 50 ).
Reference Input and R SET
G
R
A
Y
SC
92.5 IRE
A
LE
BLACK LEVEL 7.5 IRE BLANK LEVEL 40 IRE SYNC LEVEL
An external 1.235 V voltage reference is preferred to set up the analog outputs of the ADV7129. The reference voltage is connected to the VREF input. In the absence of an external reference, the on-chip voltage reference is internally connected to the VREF pin. The internal reference will set up the DAC currents, although with slightly less accuracy.
Figure 11. Composite Video Waveform SYNC Decoded; Pedestal = 7.5 IRE
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Table I. Video Output Truth Table (RSET = 398 , RLOAD = 37.5 )
Description WHITE LEVEL VIDEO VIDEO to BLANK BLACK LEVEL BLACK to BLANK BLANK LEVEL SYNC LEVEL
O/P with Sync Enabled (mA) 26.67 Video + 9.05 Video + 1.44 9.05 1.44 7.62 0
O/P with Sync Disabled (mA) 19.05 Video + 1.44 Video + 1.44 1.44 1.44 0 0
SYNC 1 1 0 1 0 1 0
BLANK 1 1 1 1 1 0 0
DAC Input Data FFH Data Data 00H 00H xxH xxH
Table II. Video Output Truth Table (RSET = 560
, RLOAD = 25
)
Description WHITE LEVEL VIDEO VIDEO to BLANK BLACK LEVEL BLACK to BLANK BLANK LEVEL SYNC LEVEL
O/P with Sync Enabled (mA) 40 Video + 13.6 Video + 2.16 13.6 2.14 11.44 0
O/P with Sync Disabled (mA) 28.57 Video + 2.14 Video + 2.14 2.14 2.14 0 0
SYNC 1 1 0 1 0 1 0
BLANK 1 1 1 1 1 0 0
DAC Input Data FFH Data Data 00H 00H xxH xxH
Table III. Video Output Truth Table (RSET = 280
, RLOAD = 25
)
Description WHITE LEVEL VIDEO VIDEO to BLACK BLACK LEVEL
O/P with Sync Disabled (mA) 52.8 Video + 0 Video + 0 0
SYNC 0 0 0 0
BLANK 0 0 0 0
DAC Input Data FFH Data Data xxH
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ADV7129
APPENDIX I BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7129 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design such that high speed, accurate performance is achieved. The "Recommended Analog Circuit Layout" (see Figure 12) shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7129 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should by minimized so as to minimize inductive ringing.
Ground Planes
the designer should pay close attention to reducing power supply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane.
Digital Signal Interconnect
The digital inputs to the ADV7129 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7129 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane.
Analog Signal Interconnect
The ground plane should encompass all ADV7129 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7129, the analog output traces, and all the digital signal traces leading up to the ADV7129. The analog ground plane should be separated from the system ground plane by a ferrite bead.
Power Planes
The ADV7129 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. Digital Inputs, especially Pixel Data Inputs and clocking signals (LOADOUT, LOADIN, etc.) should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the analog outputs should each have a 50 load resistor connected to GND. These resistors should be placed as close as possible to the ADV7129 so as to minimize reflections. There are a number of precautions that the user can take to minimize the effects of data feedthrough. a. Apply external filtering to the DAC outputs. b. Reduce input voltage risetime. From experiments, it has been seen that a reduction from 2 ns to 4 ns gives significant improvement. c. Reduce input voltage swing. A reduction from 5 V to 3 V gives significant improvement. d. Use series resistors on the pixel inputs (e.g., 100 ). e. The part can be run at 2x DAC current levels as shown in the DAC output. The differential outputs can then be connected through a differential to single balun transformer to eliminate common-mode noise. A phase splitter should be used to reduce the 2x levels to 1x at the monitor end.
The ADV7129 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7129. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7129 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode.
Supply Decoupling
For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 F ceramic capacitor decoupling. Each group of VAA pins on the ADV7129 must have at least one 0.1 F decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7129 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used,
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ADV7129
(REPEATED FOR EACH GROUP OF VAA PINS) 0.1F VAA 0.1F VAA VREF 192 PIXEL DATA RBIAS GBIAS BBIAS EACH 0.01F VAA 0.01F +5V(VAA) ANALOG POWER PLANE VAA FERRITE BEAD 10F +5V 33F (BOARD SUPPLY VCC)
ADV7129
BLANK VSYNC HSYNC CSYNC ODD/EVEN LOADIN LOADOUT VAA 0.1F 100 0.01F LPF RRSET GRSET BRSET IOR CLOCK (45MHz) IOR IOG IOG IOB IOB RCOMP GCOMP BCOMP
EACH 0.01F VAA
AN OPTIONAL BALUN TRANSFORMER CAN BE USED ON VIDEO AND COMPLEMENTARY OUTPUTS FOR IMPROVED PERFORMANCE MONITOR (CRT)
EACH 280
50
50
50
50
50
50
SENSE/SYNCOUT GND ANALOG GROUND PLANE (DOESN'T SHOW MPU PORT FOR CLARITY) FERRITE BEAD BOARD GROUND
DIGITAL GROUND PLANE
Figure 12. Typical Connection Diagram
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ADV7129
APPENDIX II THERMAL AND ENVIRONMENTAL CONSIDERATIONS
The ADV7129 is a very highly integrated monolithic silicon device. This high level of integration inevitably leads to consideration of thermal and environmental conditions which the ADV7129 must operate in. Reliability of the device is enhanced by keeping it as cool as possible. In order to avoid destructive damage to the device, the absolute maximum junction temperature must never be exceeded. Certain applications, depending on ambient temperature and pixel data rates may require forced air cooling or external heatsinks. The following data is intended as a guide in evaluating the operating conditions of a particular application so that optimum device and system performance is achieved. It should be noted that information on package characteristics published herein may not be the most up to date at the time of reading this. Advances in package compounds and manufacture will inevitably lead to improvements in the thermal data. Please contact your local sales office for the most up-to-date information.
Package Characteristics
ture stays within prescribed limits, the addition of an external heatsink can be used if the junction temperature is brought beyond the maximum limit. Junction-to-Ambient (JA) Thermal Resistance for this particular part is: JA = 25.9C/W (Still Air) JA = will significantly decrease in air flow.
Thermal Model
The junction temperature of the device in a specific application is given by: TJ = TA + PD (JC + CA) or TJ = TA + PD (JA) where: TJ = TA = PD = JC = CA = JA = Junction Temperature of Silicon (C) Ambient Temperature (C) Power Dissipation (W) Junction to Case Thermal Resistance (C/W) Case to Ambient Thermal Resistance (C/W) Junction to Ambient Thermal Resistance (C/W) (2) (1)
Junction-to-Case (JC) Thermal Resistance for this particular part is: JC = 8.9C/W (Note: JC is independent of airflow.) The maximum silicon junction temperature should be limited to 100C. Temperatures greater than this will reduce long-term device reliability. To ensure that the silicon junction tempera-
VAA = +5V 550 525
CURRENT - mA
500 475 450
425
160
200
240 280 SPEED - MHz
320
360
Figure 13. Supply Current vs. Frequency
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ADV7129
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
304-Lead Plastic Quad Flatpack (S-304)
0.167 (4.23) NOM 1.677 (42.60) NOM 1.579 (40.10) 1.571 (39.90)
228 229 153
SEATING PLANE
ROW C
152
0.0197 (0.50) NOM
ROW D
TOP VIEW (PINS DOWN)
1.579 (40.10) 1.571 (39.90) ROW B 1.677 (42.60) NOM
0.008 (0.20) NOM
PIN 1 IDENTIFIER
304 1
ROW A
76
77
0.150 (3.80) NOM
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C2215-6-10/96
PRINTED IN U.S.A.

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